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4-bit single-chip microcomputer mos integrated circuit document no. ic-3189 the mark h shows the major revised points. (o.d. no. ic-8696) date published january 1994p printed in japan ? nec corporation 1994 m pd75p316b description the m pd75p316b is a product of the m pd75316b with its built-in rom having been replaced with the one- time prom. it is most suitable for test production during system development and for production in small amounts since it can operate under the same supply voltage as mask products. the one-time prom product is capable of writing only once and is effective for production of many kinds of sets in small quantities and early startup. the eprom product allows programs to be written and rewritten, making it ideal for system evaluation. functions are described in detail in the following user's manual, which should be read when carrying out design work. m pd75308 user's manual: iem-5016 features compatible (excluding mask option) with the m pd75312b/75316b (mask products) memory capacity ? program memory (prom) : 16256 8 bits ? data memory (ram) : 1024 4 bits ? ideal for small set as camera, etc. data sheet ordering information ordering code package internal rom quality grade m pd75p316bgc-3b9 80-pin plastic qfp ( n n 14 mm) one-time prom standard m pd75p316bgk-be9 80-pin plastic qfp (fine pitch) ( n n 12 mm) one-time prom standard m pd75p316bkk-t * 80-pin ceramic wqnf (lcc with window) eprom not applicable (for function evaluation) * under development please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. the information in this document is subject to change without notice. the m pd75p316b eprom product does not provide a level of reliability suitable for use as a volume production product for customers' devices. the eprom product should be used solely for function evaluation in experiments or preproduction. in descriptions common to one-time prom products and eprom products in this document, the term "prom" is used.
m pd75p316b 2 pin configuration (top view) ? 80-pin plastic qfp ( n n 14 mm) ? 80-pin plastic tqfp (fine pitch)( n n 12 mm) ? 80-pin ceramic wqfn (lcc with window) * in normal operation, v pp input should be the v dd level. p00-03 : port 0 v lc0-2 : lcd power supply 0-2 p10-13 : port 1 bias : lcd power supply bias control p20-23 : port 2 lcdcl : lcd clock p30-33 : port 3 sync : lcd synchronization p40-43 : port 4 ti0 : timer input 0 p50-53 : port 5 pto0 : programmable timer output 0 p60-63 : port 6 buz : buzzer clock p70-73 : port 7 pcl : programmable clock bp0-7 : bit port int0, 1, 4 : external vectored interrupt 0, 1, 4 kr0-7 : key return int2 : external test input 2 sck : serial clock x1, 2 : main system clock oscillation 1, 2 si : serial input xt1, 2 : subsystem clock oscillation 1, 2 so : serial output md0-3 : mode selection sb0, 1 : serial bus 0, 1 v dd : positive power supply reset : reset input v ss : ground s0-31 : segment output 0-31 v pp : programing/verifying power com0-3 : common output 0-3 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 12 s31/bp7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 48 47 46 45 44 43 42 41 49 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 s19 s23 s22 s21 p60/kr0 p33/md3 p32/md2 p31/sync/md1 p30/lcdcl/md0 p23/buz p22/pcl p21 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si/sb1 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 s11 s2 s3 s10 s9 s8 s7 s6 s5 s4 s1 s0 reset p73/kr7 p72/kr6 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 x2 x1 v pp * xt2 xt1 v dd s30/bp6 s29/bp5 s28/bp4 s27/bp3 s26/bp2 s25/bp1 s24/bp0 s20 s18 s17 s16 s15 s14 s13 s12 m pd75p316bgc-3b9 m pd75p316bgk-be9 m pd75p316bkk-t
m pd75p316b 3 m block diagram program counter (14) program memory (prom) 16256 8 bits lcd control- ler /driver s0-s23 s24/bp0 ?31/bp7 com0?om3 v lc0 ? lc2 bias lcdcl/p30 sync/p31 general reg. data memory (ram) 1024 4 bits bank sp(8) alu cy decode and control bit seq. buffer (16) 4 p00-p03 4 p10-p13 4 p20-p23 4 p30-p33 /md0-md3 port4 4 p40-p43 port5 4 p50-p53 port6 4 p60-p63 port7 4 p70-p73 port3 port2 port1 port0 24 8 4 3 f lcd reset v ss v dd cpu clock v pp stand by control system clock generator sub main clock divider clock output control x2 x1 xt2 xt1 pcl/p22 f x / 2 n basic interval timer intbt timer/event counter #0 intt0 ti0/p13 pto0/p20 watch timer intw f lcd buz/p23 serial bus interface intcsi sck/p01 so/sb0/p02 si/sb1/p03 interrupt control kr0/p60 ?r7/p73 int4/p00 int2/p12 int1/p11 int0/p10 8
m pd75p316b 4 contents 1. pin functions ......................................................................................................................................... 5 1.1 port pins ........................................................................................................................................................... 5 1.2 other pins ......................................................................................................................................................... 7 1.3 pin input/output circuits ......................................................................................................................... 9 2. differences between products in series ................................................................................ 11 3. data memory (ram) ............................................................................................................................ 12 4. program memory write and verify ............................................................................................ 14 4.1 program memory write/verify operating modes ....................................................................... 14 4.2 program memory writing procedure ............................................................................................... 15 4.3 program memory reading procedure ............................................................................................... 16 4.4 erasure procedure( m pd75p316bkk-t-only) ........................................................................................ 17 5. electrical specifications ............................................................................................................... 18 6. package information ....................................................................................................................... 39 7. recommended soldering conditions ........................................................................................ 42 appendix a. development tools ......................................................................................................... 43 appendix b. related documents ........................................................................................................ 44
m pd75p316b 5 1. pin functions 1.1 port pins (1/2) input input/output input/output input/output input input/output input/output input/output input/output p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 *2 p31 *2 p32 *2 p33 *2 p40 to p43 *2 p50 to p53 *2 p60 p61 p62 p63 p70 p71 p72 p73 dual-function pin int4 sck so/sb0 si/sb1 int0 int1 int2 ti0 pto0 pcl buz lcdcl md0 sync md1 md2 md3 kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 i/o circuit type *1 b f - a f - b m - c b - c e - b e - b m - a m - a f - a f - a input input input input high impedance high impedance input input 4-bit input port (port0) internal pull-up resistor specification by software is possible for p01 to p03 as a 3-bit unit. 4-bit input port (port1) internal pull-up resistor specification by software is possible as a 4-bit unit. 4-bit input/output port (port2) internal pull-up resistor specification by software is possible as a 4-bit unit. programmable 4-bit input/output port (port3) input/output settable bit-wise. internal pull-up resistor specification by software is possible as a 4-bit unit. n-ch open-drain 4-bit input/output port (port 4). data input/output pins for program memory (prom) write/verify (low-order 4 bits). n-ch open-drain 4-bit input/output port (port 5) data input/output pins for program memory (prom) write/verify (high-order 4 bits). programmable 4-bit input/output port (port6). input/output settable bit-wise. internal pull-up resistor specification by software is possible as a 4-bit unit. 4-bit input/output port (port7). internal pull-up resistor specification by software is possible as a 4-bit unit. with noise elimination circuit pin name input/output function 8-bit i/o afer reset input/output input/output *1. : indicates a schmitt-triggered input. 2 . direct led drive capability.
m pd75p316b 6 1.1 port pins (2/2) bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 dual- function pin s24 s25 s26 s27 s28 s29 s30 s31 i/o circuit type g - c * 1-bit output port (bit port) dual-function as segment output pins. output output pin name input/output function 8-bit i/o after reset * for bp0 to bp7, v lc1 is selected as the input source. the output level depends on bp0 to bp7 and the v lc1 external circuit, however. h
m pd75p316b 7 1.2 other pins input input input input input input input input input external event pulse input pin for timer/event counter. timer/event counter output pin clock output pin fixed frequency output pin (for buzzer or system clock trimming) serial clock input/output pin serial data output pin serial bus input/output pin serial data input pin serial bus input/output pin edge-detected vectored interrupt input pin (rising or falling edge detection). edge-detected vectored interrupt input pin (detection edge selectable) edge-detected testable input pin (rising edge detection) testable input/output pins (parallel falling edge detection) testable input/output pins (parallel falling edge detection) main system clock oscillation crystal/ceramic connection pins. when an external clock is used, the clock is input to x1 and the inverted clock to x2. subsystem clock oscillation crystal connection pins when an external clock is used, the clock is input to xt1 and the inverted clock toxt2. xt1 can be used as a 1-bit input (test) pin. system reset input pin (low-level active). mode selection pin for program memory (prom) write/ verify. program voltage application pin for program memory (prom) write/verify . connected to v dd in normal operation. applies +12.5 v in program memory write/ verify. positive power supply pin gnd potential pin dual- function pin p13 p20 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60 to p63 p70 to p73 p30 to p33 pin name input/output function after reset input output input/output input/output input/output input/output input/output input input input input/output input/output input input input input/output i/o circuit type *1 b - c e - b e - b e - b f - a f - b m - c b b - c b - c f - a f - a b e - b s0 to s23 s24 to s31 com0 to com3 v lc0 to v lc2 bias lcdcl*2 sync*2 output output output input/output input/output bp0 to 7 p30 p31 segment signal output pins segment signal output pins common signal output pins lcd drive power supply pins external split cutting output pin external extension driver drive clock output pin external extension driver synchronization clock output pin *3 *3 *3 high impedance input input g - a g - a g - b e - b e - b ti0 pto0 pcl buz sck so/sb0 si/sb1 int4 int0 int1 int2 kr0 to kr3 kr4 to kr7 x1, x2 xt1, xt2 reset md0 to md3 v pp v dd v ss
m pd75p316b 8 *1. : indicates a schmitt-triggered input. 2. pins provided for future system expansion. currently used only as pins 30 and 31. 3. v lcx shown below can be selected for display outputs. s0 to s31: v lc1 , com0 to com2: v lc2 , com3: v lc0 however, display output levels depend on the display output and v lcx external circuit.
m pd75p316b 9 1.3 pin input/output circuits the input/output circuits for each of the pin m pd75p316b are shown below in partially simplified form. p-ch v dd out n-ch data output disable schmitt-trigger input with hysteresis characteristic p-ch v dd in n-ch p.u.r. p-ch in/out p.u.r. enable data output disable type d type a p.u.r. : pull-up resistor v dd p.u.r. p-ch in/out p.u.r. enable data output disable type d type b p.u.r. : pull-up resistor v dd cmos standard input buffer push-pull output that can be made high-impedance output (p-ch and n-ch off) type a (for type e-b) type d (for type e-b, f-a) type b type e-b type f-a type b-c in in p-ch p.u.r. p.u.r. enable v dd p.u.r. : pull-up resistor
m pd75p316b 10 n-ch p-ch out seg data p-ch v lc0 v lc1 v lc2 n-ch v lc0 v lc1 v lc2 com data n-ch p-ch p-ch n-ch out n-ch p-ch type f-b type g-o type m-a type g-a type g-b type m-c p.u.r. in/out p.u.r. enable output disable (p) output disable data output disable (n) v dd v dd p-ch n-ch p-ch p.u.r. : pull-up resistor h in/out n-ch (+10 v withstand voltage) data output disable middle-high voltage input buffer (+10 v withstand voltage) n-ch p-ch out p-ch n-ch v dd v lc0 v lc1 v lc2 seg data/ bit port data p.u.r. enable in/out p-ch v dd n-ch data output disable p.u.r. : pull-up resistor p.u.r.
m pd75p316b 11 2. differences between products in series the m pd75p316b is a version of the m pd75316b with its built-in mask rom replaced with the one-time prom or eprom. when performing debugging or preproduction of an application system using prom and then volume production using a mask rom product, etc., these differences should be taken into account in the transition. table 2-1 shows the differences from the other products in series. for the details of the cpu functions and the built-in hardware, please refer to the m pd75308 user's manual (iem-5016) . product name comparison item ? 80-pin plastic qfp ( n n 14 mm) ? 80-pin plastic tqfp (fine pitch)( n n 12 mm) ? 80-pin plastic qfp ( n n 14 mm) ? 80-pin plastic tqfp (fine pitch)( n n 12 mm) ? 80-pin ceramic qwfn (lcc with window) table 2-1 differences between products in series m pd75p316a m pd75p316b m pd75312b/75316b program memory (bytes) ? eprom/one-time prom ? one-time prom ? mask rom ? 16256 ? eprom ? 12160/16256 ? 16256 data memory (x 4 bits) 1024 pull-up resistors of ports 4 and 5 none incorporation specifiable by mask option lcd driving power supplying split none incorporation specifiable resistor by mask option pin connection no.50 to 55 p30/md0 to p33/md3 p30 to p33 no.57 v pp ic the mask rom products and prom products have different consumption electrical specifications currents, etc. see the electrical specifications section in the relevant data sheets for details. power supply voltage range 2.7 to 6.0 v 2.0 to 5.5 v ? 80-pin plastic qfp (14 20 mm) package ? 80-pin ceramic wqnf (lcc with window) other the mask rom products and prom products have different circuit scales and mask layouts, and therefore differ in terms of noise resistance and noise radiation. * noise resistance and noise radiation differs between the prom products and mask rom products. when investigating a switch from prom product to mask prom product in the transition from preproduction to volume production, thorough evaluation should be carried out with the mask rom cs product (not the es product). h h h h
m pd75p316b 12 3. data memory (ram) fig. 3-1 shows the data memory configuration. it consists of a data area and a peripheral hardware area. the data area consists of memory banks 0 to 3 with each bank consisting of 256 words x 4 bits. peripheral hardware has been assigned to the area of memory bank 15. (1) data area the data area comprises a static ram. it is used to store program data and as a subroutine, interrupt execution stack memory. even if the cpu operation is stopped in the standby mode, it is possible to hold the memory content for a long time by battery backup, etc. the data area is operated by memory manipulation instructions. the static ram has been mapped to memory banks 0, 1, 2 and 3 by 256 x 4 bits each. bank 0 has been mapped as a data area but is also available as a general register area (000h to 007h) and a stack area (000h to 0ffh) (banks 1, 2 and 3 are available only as a data area). in the static ram, 1 address consists of 4 bits. it can be operated in units of 8 bits by 8-bit memory ma- nipulation instructions or in bits by bit manipulation instructions, however. in an 8-bit manipulation instruc- tion, an even address should be specified. (a) general register area the general register area can be operated either by general register operation instructions or by memory manipulation instructions. up to eight 4-bit registers are available. that part of the 8 general registers which is not used in the program is available as a data area or a stack area. (b) stack area the stack area is set by an instruction. it is available as a subroutine execution or interrupt service execution save area. (2) peripheral hardware area the peripheral hardware area has been mapped to f80h to fffh of memory bank 15. it is operated by memory manipulation instructions just as the static ram. in the peripheral hardware, however, the operable bit unit differs from one address to another. an address to which peripheral hardware has not been assigned is inaccessible since no data memory is built in.
m pd75p316b 13 fig. 3-1 data memory map 256 4 128 4 (8 4) data memory not on-chip memory bank f80h fffh peripheral hardware area general register area 3ffh 300h 2ffh 200h 1ffh 100h 0ffh 008h 007h 000h data area static ram (1024 4) stack area 256 4 256 4 256 4 0 1 2 3 15
m pd75p316b 14 4. program memory write and verify the rom built into the m pd75p316b is a 16256 x 8-bit electrically writable one-time prom. the table below shows the pins used to program this prom. there is no address input; instead, a method to update the ad- dress by the clock input via the x1 pin is adopted. function voltage applecation pin for program memory write/verify (normally v dd potential). address update clock inputs for program memory write/ verify. inverse of x1 pin signal is input to x2 pin. operating mode selection pin for program memory write/ verify. 8-bit data input/output pins for progrm memory write/ verify. supply voltage application pin. applies 2.0 to 5.5 v in normal operation, and 6 v for program memory write/verify. pin name v pp x1, x2 md0 to md3 p40 to p43 (low-order 4 bits) p50 to p53 (high-order 4 bits) v dd 4.1 program memory write/verify operating modes the m pd75p316b assumes the program memory write/verify mode when +6 v and +12.5 v are applied respectively to the v dd and v pp pins. the table below shows the operating modes available by the md0 to md3 pin setting in this mode. all the remaining pins are at the v ss potential by the pull-down resistor. v pp +12.5 v v dd +6 v md0 h l l h md1 l h l x md2 h h h h md3 l h h h operating mode program memory address zero-clear write mode verify mode program inhibit mode operating mode setting x: l or h
m pd75p316b 15 4.2 program memory writing procedure the program memory writing procedure is shown below. high-speed write is possible. (1) pull down a pin which is not used to v ss via the resistor. the x1 pin is at the low level. (2) supply 5 v to the v dd and v pp pins. (3) 10 m s wait. (4) the program memory address 0 clear mode. (5) supply 6 v and 12.5 v respectively to v dd and v pp . (6) the program inhibit mode. (7) write data in the 1-ms write mode. (8) the program inhibit mode. (9) the verify mode. if written, proceed to (10); if not written, repeat (7) to (9). (10) (number of times written in (7) to (9): x) x 1-ms additional write. (11) the program inhibit mode. (12) update (+1) the program memory address by inputting 4 pulses to the x1 pin. (13) repeat (7) to (12) up to the last address. (14) the program memory address 0 clear mode. (15) change the v dd and v pp pins voltage to 5 v. (16) power off. the diagram below shows the procedure of the above (2) to (12). data input data input write verify additional write address increment repeated x times data output v pp v pp v dd v dd v dd + 1 v dd x1 p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33)
m pd75p316b 16 4.3 program memory reading procedure the m pd75p316b can read the content of the program memory in the following procedure. it reads in the verify mode. (1) pull down a pin which is not used to v ss via the resistor. the x1 pin is at the low level. (2) supply 5 v to the v dd and v pp pins. (3) 10 m s wait. (4) the program memory address 0 clear mode. (5) supply 6 v and 12.5 v respectively to v dd and v pp . (6) the program inhibit mode. (7) the verify mode. if clock pulses are input to the x1 pin, data is output sequentially 1 address at a time at the period of inputting 4 pulses. (8) the program inhibit mode. (9) the program memory address 0 clear mode. (10) change the v dd and v pp pins voltage to 5 v. (11) power off. the diagram below shows the procedure of the above (2) to (9). data output data output p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) "l" v pp v pp v dd v dd v dd + 1 v dd x1
m pd75p316b 17 4.4 erasure procedure ( m pd75p316bkk-t only) the data programmed in the m pd75p316b can be erased by exposure to ultraviolet radiation through the window in the top of the package. erasure is possible using ultraviolet light with a wavelength of approximately 250 nm. the exposure re- quired for complete erasure is 15 w.s/cm 2 (uv intensity x erasure time). erasure takes aproximately 15 to 20 minutes using a commercially available uv lamp (254 nm wavelength, 12 mw/cm 2 intensity). note 1. program contents may also be erased by extended exposure to direct sunlight or fluorescent light. the contents should therefore be protected by masking the window in the top of the package with light-shielding film. the light-shielding film provided with nec's uv eprom products should be used. 2. erasure should normally be carried out at a distance of 2.5 cm or less from the uv lamp. remarks the erasure time may be increased due to deterioration of the uv lamp or dirt on the package window.
18 m pd75p316b 5. electrical specifications absolute maximum ratings (ta = 25 c) i oh i oh * * the r.m.s. value should be calculated as follows [r.m.s. value] = [peak value] x duty note product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. in other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. capacitance (ta = 25 c, v dd = 0 v) f=1 mhz unmeasured pins returned to 0 v. parameter symbol test conditions rating unit v dd C0.3 to + 7.0 v v i1 except ports 4 & 5 C0.3 to v dd + 0.3 v v i2 ports 4 & 5 C0.3 to + 11 v v o C0.3 to v dd + 0.3 v 1 pin C15 ma all pins C30 ma 1 pin peak value 30 ma r.m.s. value 15 ma total for ports 0, 2, 3, 5 peak value 100 ma r.m.s. value 60 ma total for ports 4, 6, 7 peak value 100 ma r.m.s. value 60 ma t opt C40 to + 85 c t stg C65 to + 150 c supply voltage input voltage output voltage output current high output current low operating temperature storage temperature typ. max. 15 15 15 unit pf pf pf min. parameter input capacitance output capacitance i/o capacitance test conditions symbol c in c out c io
19 m pd75b316b main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) resonator ceramic resonator *3 crystal *3 external clock unit mhz ms mhz ms ms mhz ns *1. the oscillation frequency and x1 input frequency are only indications of the oscillator characteristics. see the ac characteristics for instruction execution times. 2. the oscillation stabilization time is the time required for oscillation to stabilize after v dd reaches the min. value of the oscillation voltage range, or the stop mode is released. 3. when the oscillation frequency is 4.19 mhz < f xx <= 5.0mhz, pcc = 0011 should not be selected as the instruction execution time. if pcc = 0011 is selected, one machine cycle will be less than 0.95 us, and the min. value of 0.95 us in the specification will not be achieved. note when the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. keep away from lines carrying a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v dd . do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. max. 5.0 *3 4 5.0 *3 10 30 5.0 *3 500 typ. 4.19 min. 1.0 1.0 1.0 100 test conditions after v dd has reached min. of oscillation voltage range. v dd =4.5 to 6.0 v parameter oscillation frequency (f xx ) *1 oscillation stabilization time *2 oscillation frequency (f xx ) *1 oscillation stabilization time *2 x1 input frequency (f x ) *1 x1 input high-/low-level width (t xh , t xl ) recomended constant m pd74hcu04 v dd v dd x2 x1 c1 c2 x2 x1 c1 c2 x2 x1
20 m pd75p316b subsystem clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) recomended constant unit khz s s khz m s resonator crystal resonator external clock * this is the time required for oscillation to stabilize after v dd reaches the min. value of the oscillation voltage range. note when the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. keep away from lines carrying a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v dd . do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. max. 35 2 10 100 15 typ. 1.0 32.768 min. 32 32 5 test conditions v dd =4.5 to 6.0 v parameter oscillation frequency (f xt ) oscillation stabilization time * xt1 input frequency (f xt ) xt1 input high-/low- level width (t xth , t xtl ) v dd xt2 xt1 c1 c2 r xt2 xt1 open
21 m pd75b316b v dd C1.0 v input voltage high input voltage low v oh1 v oh2 v dd C2.0 v output voltage high 0.4 v 1.0 v i loh2 v out = 10 v 20 m a i lih3 v in = 10 v 20 m a v ol2 sb0, 1 0.2 v dd v (1) v dd =2.7 to 6.0 v dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit v ih1 ports 2 and 3 0.7 v dd v dd v v ih2 ports 0, 1, 6, 7 and reset 0.8 v dd v dd v v ih3 ports 4 and 5 0.7 v dd 10 v v ih4 x1, x2, xt1 v dd C0.5 v dd v v il1 ports 2, 3, 4, 5 0 0.3 v dd v v il2 ports 0, 1, 6, 7 and reset 0 0.2 v dd v v il3 x1, x2, xt1 0 0.4 v v dd = 4.5 to 6.0 v ports 0, 2, 3, 6, 7, i oh = C1 ma and bias i oh = -100 m av dd C0.5 v v dd = 4.5 to 6.0 v bp0 to bp7 i oh = C100 m a (with 2 i oh outputs) i oh = C30 m av dd C1.0 v ports 3, 4, 5 v dd = 4.5 to 6.0 v 0.7 2.0 v i ol = 15 ma ports 0, 2, 3, 4, 5, 6, 7 v dd = 4.5 to 6.0 v v ol1 i ol = 1.6 ma i ol = 400 m a 0.5 v openCdrain pull-up resistor 3 1 k w v dd = 4.5 to 6.0 v bp0 to bp7 i ol = 100 m a (with 2 i ol outputs) i ol = 50 m a 1.0 v i l1h1 other than below 3 m a v in = v dd i lih2 x1, x2, xt1 20 m a ports 4 and 5 input leakage i lil1 other than below C3 m a current low v in = 0 v i lil2 x1, x2, xt1 C20 m a output leakage i loh1 v out = v dd other than below 3 m a current high ports 4 and 5 output leakage current low output voltage low input leakage current high i lol v out = 0 v C3 m a
22 m pd75p316b dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit ports 0, 1, 2, 3, 6, 7 v dd = 5.0 v 10% 15 40 80 k w r l (except p00) v in = 0 v v dd = 3.0 v 10% 30 200 k w lcd drive voltage v lcd 2.0 v dd v lcd output voltage deviation *1 v odc i o = 5 m a0 0.2 v (common) lcd output voltage deviation v ods i o = 1 m a0 0.2 v (segment) v dd = 5 v 10% *4 4.0 12 ma i ddi 4.19 mhz *3 v dd = 3 v 10% *5 0.5 1.5 ma crystal oscillation c1 = c2 = 22 pf halt v dd = 5 v 10% 1 3 ma i dd2 mode v dd = 3 v 10% 300 900 m a i dd3 v dd = 3 v 10% 30 90 m a 32 khz *6 crystal oscillation halt v dd = 3 v 10% mode v dd = 5 v 10% 1 25 m a i dd5 0.5 15 m a ta = 25 c 0.5 5 m a *1. the voltage deviation is the difference between the output voltage and the ideal value of the common output (v lcdn ; n = 0, 1, 2). 2. excluding the current flowing in the internal pull-up resistor. 3. including the case where the subsystem clock is oscillated. 4. when the processor clock control register (pcc) is set to 0011 for operation in high-speed mode. 5. when pcc is set to 0000 for operation in low-speed mode. 6. when the system clock control register (scc) is set to 1001, main system clock oscillation is stopped, and the device is operated on the subsystem clock. internal pull-up resistor v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.7 v v lcd v dd i dd4 721 m a v dd = 3 v 10% xt1 = 0 v stop mode supply current *2
23 m pd75b316b t cy t tih , t til t inth , t intl t cy vs v dd (operating on main system clock) cycle time t cy [ m s] supply voltage v dd [v] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 30 64 70 6 guaranteed operation range ac characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit operating on main v dd = 4.5 to 6.0 v 0.95 64 m s system clock 3.8 64 m s operating on subsystem clock ti0 input v dd = 4.5 to 6.0 v 0 1 mhz frequency f ti 0 275 khz ti0 input high-/low- v dd = 4.5 to 6.0 v 0.48 m s level width 1.8 m s int0 *2 m s int1, 2, 4 10 m s kr0 to kr7 10 m s reset low-level t rsl 10 m s width 114 122 125 m s interrupt input high-/low-level width *1. the cpu clock ( f ) cycle time (minimum instruc- tion execution time) is determined by the oscil- lation frequency of the connected resonator, the system clock control register (scc), and the processor control register (pcc). the graph on the right shows the characteristic of the cycle time t cy against the supply current v dd in the case of main system clock operation. 2. 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). cpu clock cycle time *1 (minimum instruction execution time = 1 machine cycle)
24 m pd75p316b t sik2 100 ns serial transfer operations 2-wired and 3-wired serial i/o modes (sck ... internal clock output): (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 1600 ns sck cycle time t kcy1 3800 ns sck high-/low-level v dd = 4.5 to 6.0 v t kcy1 /2-50 ns width t kcy1 /2-150 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 250 ns delay time t kso1 from sck 1000 ns 2-wired and 3-wired serial i/o modes (sck ... external clock input): (ta = -40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy2 3200 ns sck high-/low-level v dd = 4.5 to 6.0 v 400 ns width 1600 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 300 ns delay time t kso2 from sck 1000 ns * r l and c l are the so output line load resistance and load capacitance. t sik1 150 ns t ksi1 400 ns t kl1 t kh1 t ksi2 400 ns t kl2 t kh2 * r l = 1 k w , c l = 100 pf * r l = 1 k w , c l = 100 pf
25 m pd75b316b sbi mode (sck ... internal clock output (master)): (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 1600 ns t kcy3 3800 ns sck high-/low-level v dd = 4.5 to 6.0 v t kcy3 /2-50 ns width t kcy3 /2-150 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output v dd = 4.5 to 6.0 v 0 250 ns delay time from t kso3 sck 0 1000 ns sb0, 1 from sck - t ksb t kcy3 ns sck from sb0, 1 t sbk t kcy3 ns t sbl t kcy3 ns t sbh t kcy3 ns sbi mode (sck ... external clock input (slave)): (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy4 3200 ns sck high-/low-level v dd = 4.5 to 6.0 v 400 ns width 1600 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output v dd = 4.5 to 6.0 v 0 300 ns delay time from t kso4 sck 0 1000 ns sb0, 1 from sck - t ksb t kcy4 ns sck from sb0, 1 t sbk t kcy4 ns t sbl t kcy4 ns t sbh t kcy4 ns * r l and c l are the sb0, 1 output line load resistance and load capacitance. t sik3 150 ns t ksi3 t kcy3 /2 ns t kl3 t kh3 sb0, 1 low-level width sb0, 1 high-level width t ksi4 t kcy4 /2 ns t sik4 100 ns t kl4 t kh4 r l = 1 k w , * c l = 100 pf r l = 1 k w , * c l = 100 pf sb0, 1 high-level width sb0, 1 low-level width
26 m pd75p316b (2) v dd =2.7 to 6.0 v dc characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit v ih1 ports 2 and 3 0.8 v dd v dd v v ih2 ports 0, 1, 6, 7 and reset 0.8 v dd v dd v v ih3 ports 4 and 5 0.8v dd 10 v v ih4 x1, x2, xt1 v dd C0.3 v dd v v il1 ports 2, 3, 4, 5 0 0.2 v dd v v il2 ports 0, 1, 6, 7 and reset 0 0.2 v dd v v il3 x1, x2, xt1 0 0.25 v ports 0, 2, 3, 6, 7 and bias bp0 to bp7 (with 2 i oh outputs) ports 0, 2, 3, 4, 5 6, 7 v ol1 openCdrain, pull-up resistor 1 k w bp0 to bp7 (with 2 i ol outputs) i lih1 other than below 3 m a v in = v dd i lih2 x1, x2, xt1 20 m a ports 4 and 5 input leakage i lil1 other than below C3 m a current low v in = 0 v i lil2 x1, x2, xt1 C20 m a output leakage i loh1 v out = v dd other than below 3 m a current high i loh2 v out = 10 v ports 4 and 5 20 m a output leadage i lol v out = 0 v C3 m a current low ports 0, 1, 2, 3, 6, 7 r l (except p00) v dd = 2.5 v 10% 50 600 k w v in = 0 v lcd drive voltage v lcd 2.0 v dd v input voltage high input voltage low v oh2 i oh = C10 m av dd C0.4 v v oh1 i oh = C100 m av dd C0.5 v output voltage high i ol = 400 m a 0.5 v sb0, 1 0.2 v dd v output voltage low v ol2 i ol = 10 m a 0.4 v input leakage current high i lih3 v in = 10 v 20 m a internal pull-up resistor
27 m pd75b316b dc characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) v lcdo = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.0 v v lcd v dd 4.19 mhz *3 crystal oscillation c1 = c2 = 22 pf low-speed mode 32 khz *5 crystal oscillation xt1 = 0 v stop mode v dd = 2.5 v 10% parameter symbol test conditions min. typ. max. unit lcd output voltage deviation *1 v odc i o = 5 m a0 0.2 v (common) lcd output voltage deviation v ods i o = 1 m a0 0.2 v (segment) v dd = 3 v 10% *4 0.5 1.5 ma i ddi v dd = 2.5 v 10% *4 0.4 1.2 ma halt v dd = 3 v 10% 300 900 m a i dd2 mode v dd = 2.5 v 10% 200 600 m a v dd = 3 v 10% 40 90 m a i dd3 supply current *2 v dd = 2.5 v 10% 25 75 m a halt v dd = 3 v 10% 7 21 m a i dd4 mode v dd = 2.5 v 10% 4 12 m a 0.5 15 m a v dd = 3 v 10% ta = 25 c 0.5 5 m a i dd5 0.4 15 m a ta = 25 c 0.4 5 m a *1. the voltage deviation is the difference between the output voltage and the ideal value of the common output (v lcdn ; n = 0, 1, 2). 2. excluding the current flowing in the internal pull-up resistor. 3. including the case where the subsystem clock is oscillated. 4. when pcc is set to 0000 for operation in low-speed mode. 5. when the system clock control register (scc) is set to 1001, main system clock oscillation is stopped, and the device is operated on the subsystem clock.
28 m pd75p316b 1.8 m s 3.4 64 m s f ti 0 275 khz t inth , t intl *1. the cpu clock ( f ) cycle time (minimum instruc- tion execution time) is determined by the oscil- lation frequency of the connected resonator, the system clock control register (scc), and the processor clock control register (pcc). the graph on the right shows the characteristic of the cycle time t cy against the supply current v dd in the case of main system clock operation. 2. 2t cy or 128/f x depending on the setting of the interrupt mode register (imo). t cy vs v dd (operating on main system clock) cycle time t cy [ m s] supply voltage v dd [v] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 30 64 70 6 guaranteed operation range 114 122 125 m s ac characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 6.0 v 3.8 64 m s operating on main v dd = 2.0 to 6.0 v 5 64 m s system clock t cy ta = C40 to + 60 c v dd = 2.2 to 6.0 v operating on subsystem clock ti0 input frequency ti0 input high-/low- t tih , level width t til int0 *2 m s int1, 2, 4 10 m s kr0 to kr7 10 m s reset low-level t rsl 10 m s width interrupt input high-/low-level width cpu clock cycle time (minimum instruc- tion execution time = 1 machine cycle) *1
29 m pd75b316b serial transfer operations 2-wired and 3-wired serial i/o mode (sck ... internal clock output): (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 1600 ns t kcy1 3800 ns sck high-/low- v dd = 4.5 to 6.0 v t kcy1 /2-50 ns level width t kcy1 /2-150 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 250 ns delay time t kso1 from sck 1000 ns 2-wired and 3-wired serial i/o mode (sck ... external clock input): (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy2 3200 ns sck high-/low- v dd = 4.5 to 6.0 v 400 ns level width 1600 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 300 ns delay time t kso2 from sck 1000 ns * r l and c l are the so output line load resistance and load capacitance. t ksi2 400 ns t sik2 100 ns t kl1 t kh1 t ksi1 400 ns t sik1 250 ns r l = 1 k w , c l = 100 pf * t kl2 t kh2 r l = 1 k w , c l = 100 pf *
30 m pd75p316b t sik4 100 ns t ksi4 t kcy4 /2 ns t kl4 t kh4 r l = 1 k w , c l = 100 pf * sbi mode (sck ... internal clock output (master)): (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 1600 ns t kcy3 3800 ns sck high-/low- v dd = 4.5 to 6.0 v t kcy3 /2-50 ns level width t kcy3 /2-150 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output v dd = 4.5 to 6.0 v 0 250 ns delay time t kso3 from sck 0 1000 ns sb0, 1 from sck - t ksb t kcy3 ns sck from sb0, 1 t sbk t kcy3 ns t sbl t kcy3 ns t sbh t kcy3 ns sbi mode (sck ... external clock input (slave)): (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy4 3200 ns sck high-/low- v dd = 4.5 to 6.0 v 400 ns level width 1600 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 v dd = 4.5 to 6.0 v 0 300 ns output delay t kso4 time from sck 0 1000 ns sb0, 1 from sck - t ksb t kcy4 ns sck from sb0, 1 t sbk t kcy4 ns t sbl t kcy4 ns t sbh t kcy4 ns * r l and c l are the sbo, 1 output line load resistance and load capacitance. t ksi3 t kcy3 /2 ns t sik3 250 ns t kl3 t kh3 r l = 1 k w , c l = 100 pf * sb0, 1 low-level width sb0, 1 high-level width sb0, 1 low-level width sb0, 1 high-level width
31 m pd75b316b x1 input 1/f x t xl t xh v dd -0.5 v 0.4 v xt1 input 1/f xt t xtl t xth v dd -0.5 v 0.4 v ti0 1/f ti t til t tih ac timing test points (except x1 and xt1 inputs) clock timings ti0 timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points
32 m pd75p316b sck t kcy1 t kh1 t kl1 input data output data t sik1 t ksi1 t kso1 si so serial transfer timing 3-wired serial i/o mode: 2-wired serial i/o mode: t kso2 t kl2 t kh2 t kcy2 sck sb0,1 t sik2 t ksi2
33 m pd75b316b t intl t inth int0,1,2,4 kr0-7 t rsl reset t ksb t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1 t sbk serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing t ksb t sbl t sbh t sbk t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1
34 m pd75p316b data memory stop mode low supply voltage data retention characteristics (ta = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 2.0 6.0 v data retention supply current *1 i dddr v dddr = 2.0 v 0.3 15 m a release signal setting time t srel 0 m s oscillation stabilization release by reset 2 17 /fx ms wait time *2 t wait release by interrupt request *3 ms *1. excluding current flowing in the internal pull-up resistor. 2. the oscillation stabilization time is the time during which the cpu operation is stopped to prevent unstable operation when oscillation is started. 3. depends on the basic interval timer mode register (btm) setting ( see table below). wait time btm3 btm2 btm1 btm0 (figure in ( ) is for fx = 4.19 mhz) 0 00 2 20 /fx (approx. 250 ms) 0 11 2 17 /fx (approx. 31.3 ms) 1 01 2 15 /fx (approx. 7.82 ms) 1 11 2 13 /fx (approx. 1.95 ms)
35 m pd75b316b data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) stop mode data retention mode stop instruction execution v dd halt mode operating mode v dddr t srel t wait standby release signal (interrupt request) stop mode data retention mode stop instruction execution reset v dd internal reset operation halt mode operating mode v dddr t srel t wait
36 m pd75p316b dc programming characteristics (ta = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol test conditions min. typ. max. unit v ih1 except x1, x2 0.7 v dd v dd v v ih2 x1, x2 v dd C0.5 v dd v v il1 except x1, x2 0 0.3 v dd v v il2 x1, x2 0 0.4 v i l1 v in = v il or v ih 10 m a v oh i oh = C1 ma v dd C1.0 v v oh i ol = 1.6 ma 0.4 v v dd supply i dd 30 ma current v dd supply i pp md0 = v il , mdi = v ih 30 ma current note 1. ensure that v pp does not exeed +13.5 v including overshoot. 2. v dd must be applied before v pp , and cut after v pp . input voltage high input voltage low input leakage current output voltage high outputvoltage low
37 m pd75b316b dc programming characteristics (ta = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol *1 test conditions min. typ. max. unit address setup time *2 (to md0 )t as t as 2 m s md1 setup time (to md0 )t m1s t oes 2 m s data setup time (to md0 )t ds t ds 2 m s address hold time *2 (from md0 - )t ah t ah 2 m s data hold time (from md0 - )t dh t dh 2 m s data output float delay time from md0 - t df t df 0 130 ns v pp setup time (to md3 - )t vps t vps 2 m s v dd setup time (to md3 - )t vds t vcs 2 m s initial program pulse width t pw t pw 0.95 1.0 1.05 ms additional program pulse width t opw t opw 0.95 21.0 ms md0 setup time (to md1 - )t mos t ces 2 m s data output delay time from md0 t dv t dv md0=md1=v il 1 m s md1 hold time (from md0 - )t m1h t oeh 2 m s md1 recovery time (from md0 )t m1r t or 2 m s program counter reset time t pcr 10 m s x1 input high-/low-level width t xh , t xl 0.125 m s x1 input frequency f x 4.19 mhz initial mode setting time t i 2 m s md3 setup time (to md1 - )t m3s 2 m s md3 hold time (from md1 )t m3h 2 m s md3 setup time (to md0 )t m3sr program memory read 2 m s data output delay time from address *2 t dad t acc program memory read 2 m s data output hold time from address *2 t had t oh program memory read 0 130 m s md3 hold time (from md0 - )t m3hr program memory read 2 m s data output float delay time from md3 t dfr program memory read 2 m s *1. symbol of corresponding m pd27c256a 2. the internal address signal is incremented by 1 on the 4th rise of the x1 input, and is not connected to a pin. t m1h +t m1r 3 50 m s
38 m pd75p316b program memory write timing t vps t vds t ds t dh t 1 t pw t m1r t m0s t pcr t m1s t m1h t m3s t m3h t opw t ds t dv t df t ah t dh t as t xl t xh data input d ata output d ata i nput data input v dd v pp v pp v dd v dd + 1 v dd x1 p40 - p43 p50 - p53 md0 md1 md2 md3 program memory read timing v dd v pp v pp v dd v dd + 1 v dd x1 md0 md1 md2 md3 t vps t m3sr t xh t xl t had t dad t 1 t dv t m3hr t dfr t pcr t vds data output data output p40 - p43 p50 - p53
m pd75p316b 39 6. package information a m f b 60 61 40 k l 80 pin plastic qfp ( 14) 80 1 21 20 41 g d c detail of lead end s q p m i h j 55 n s80gc-65-3b9-3 item millimeters inches a b c d f g h i j k l 17.2 0.4 14.0 0.2 0.8 0.30 0.10 0.13 14.0 0.2 0.677 0.016 0.031 0.031 0.005 0.026 (t.p.) 0.551 note m n 0.10 0.15 1.6 0.2 0.65 (t.p.) 0.004 0.006 +0.004 C0.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.012 0.551 0.8 0.2 0.031 p 2.7 0.106 0.677 0.016 17.2 0.4 0.8 +0.009 C0.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 C0.05 +0.009 C0.008 +0.004 C0.005 +0.009 C0.008
m pd75p316b 40 80 pin plastic tqfp (fine pitch) ( 12) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.0?.2 0.551 +0.009 ?.008 b 12.0?.2 0.472 +0.009 ?.008 c 12.0?.2 0.472 +0.009 ?.008 d 14.0?.2 0.551 +0.009 ?.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.009?.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.05 0.041 q 0.05?.05 0.002?.002 r 55? 55? +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80
m pd75p316b 41 z u1 a t b d c u g f w r s q k m i h j x80kw-65a-1 item millimeters inches a b c d f g h i j k q 14.0 0.2 13.6 3.6 max. 0.06 13.6 0.551 0.008 0.072 0.142 max. 0.003 0.024 (t.p.) 0.535 note r s 0.825 0.825 0.65 (t.p.) 0.032 0.032 each lead centerline is located within 0.06 mm (0.003 inch) of its true position (t.p.) at maximum material condition. 0.018 0.535 t r 2.0 r 0.079 0.551 0.008 14.0 0.2 1.84 u 9.0 0.354 u1 2.1 0.083 +0.004 C0.005 w z 0.10 0.004 80 1 0.45 0.10 0.039 +0.007 C0.006 1.0 0.15 c 0.3 c 0.012 0.75 0.15 0.030 +0.006 C0.007 80 pin ceramic wqfn
m pd75p316b 42 7. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions for the surface mounting type, refer to the information document "surface mount technology manual (iei 1207)" . for soldering methods and conditions other than those recommended below, contact our salesman. table 7-1 recommended soldering conditions m pd75p316bgc-3b9: 80-pin plastic qfp ( n n 14 mm) soldering method recommended soldering conditions recommended condition symbol package peak temperature: 230 c; infrared reflow duration: 30 sec. max. (at 210 c or above); ir35-00-1 number of times: once; pin part heating pin part temperature: 300 c max.; duration: 3 sec. max. (per device side) m pd75p316bgk- be 9: 80-pin plastic qfp ( n n 12 mm) soldering method recommended soldering conditions recommended condition symbol package peak temperature: 235 c; duration: 30 sec. max. (at 210 c or above); infrared reflow number of times: once; ir35-00-1 timelimit: 7 days*(thereafter 10 hours prebaking required at 125 c) pin part heating pin part temperature: 300 c max.; duration: 3 sec. max. (per device side) * for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65% rh. note use of more than one soldering method should be avoided (except in the case of pin part heating).
m pd75p316b 43 appendix a. development tools the following development tools are available for system development using the m pd75p316b. hardware software ie-75000-r *1 ie-75001-r ie-7500-r-em *2 ep-75308bgc-r ev-9200gc-80 ep-75308bgk-r ev-9500gk-80 pg-1500 pa-75p316bgc pa-75p316bgk ie control program pg-1500 controller ra75x relocatable assembler 75x series in-circuit emulator emulation board for ie-75000-r and ie-75001-r emulation probe for m pd75p316bgc. provided with ev-9200gc-80, 80-pin conversion socket. m pd75p316bgk emulation probe. provided with ev-9200gk-80, 80-pin conversion socket. prom programmer m pd75p316bgc programmer adapter. connected with pg-1500. m pd75p316bgk programmer adapter. connected with pg-1500. host machine pc-9800 series (ms-dos? ver.3.30 to ver.5.00a *3 ) ibm pc/at? (pc dos? ver.3.1) *1. maintenance product 2. not incorporated in the ie-75001-r. 3. the task swap function, which is provided with ver.5.00/5.00a, is not available with this software. h
m pd75p316b 44 appendix b. related documents device related documents document name document number user's manual iem-5016 instruction application table iem-994 application note iem-5035 iem-5041 75x series selection guide if-151 development tools documents document name document number ie-75000-r/ie-75001-r user's manual eeu-846 ie-75000-r-em user's manual eeu-673 ep-75308bgc-r user's manual eeu-825 ep-75308bgk-r user's manual eeu-838 pg-1500 user's manual eeu-651 ra75x assembler package user's manual operation eeu-731 language eeu-730 pg-1500 controller user's manual eeu-704 other documents document name document number package manual iei-635 surface mount technology manual iei-1207 quality grande on nec semiconductor device iei-1209 nec semiconductor device reliability & quality control iem-5068 electrostatic discharge(esd) test mem-539 semiconductor devices quality guarantee guide mei-603 microcomputer related products guide other manufacturers volume mei-604 * the contents of the above related documents are subject to change without notice. the latest documents should be used for design, etc. hardware software
m pd75p316b 45
[memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92.6 m pd75p316b

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